Saturday, November 19, 2011

Concurrent statements

    Until now you have seen how to transform a truth table in concurrent signal assignments or in processes. But not every circuit can or should be described only with logic functions. That's why VHDL has 2 concurrent signal assignment statements:
       - conditional signal assignment
       - selected signal assignment

    In order to demonstrate these 2 statements we will design 2 circuits: a 4 to 1 multiplexer and a 2 to 4 decoder. Let's see first what these circuits do:
    4 to 1 multiplexer
    Such a circuit has 4 data inputs, 2 select inputs and 1 output:

    This is the basic I/O of any mux. The 4 inputs can be of any bit length (from 1 bit to what your design needs). The s input can also be of different bit lengths but one rule needs to be respected: number of inputs=2 to the power of s. So if you want a 2 to 1 mux you will need a 1 bit select signal. For a 4 to 1 mux the s signal needs to be 2 bits in length. The output o will receive one of the inputs based on the value of s.

       s    o
      00   i0
      01   i1
      10   i2
      11   i3
    This is the table that a multiplexer follows.

    2 to 4 decoder
    A n to 2^n decoder takes n inputs that act similarly to the s input of the mux and outputs a 2^n value based on the input value. Let's see how a decoder looks:
    The table for a decoder is:
       i       o
     00    0001
     01    0010
     10    0100
     11    1000
    The circuits works exactly as you see in this table so no further explanations are needed.

    Entity coding
    The entities for the 2 circuits should be like:
    For the mux and for the decoder:

    Conditional signal assignment
    This type of statement is not the best way to describe the 2 circuits because it is priority based but it is a good way to understand how to use it.
    The structure of the statement is:

    output <= input1 when condition1 else
                    input2 when condition2 else

    As you can see the program will evaluate the first condition and if it is true the output will get the input1 value. If condition1 is false then condition2 will be evaluated and so on. If none of the conditions are true then output will get the inputn value.
    This is the reason I recommend not to use this statement to describe multiplexers and decoders/encoders. The conditional signal assignment is best suited for priority encoders and other such circuits.

    The VHDL code for the 4 to 1 4 bit multiplexer:

    The VHDL code for the 2 to 4 decoder is:

    Selected signal assignment
    This type of assignment is the best way to describe multiplexers and decoders because they are not priority based.
    The structure of the statement is:
    with select_signal select
           output <= value1 when select_sig_value1,
                           value2 when select_sig_value2,
                          valuen when others;

    So the output will get one of the n-1 values depending on the select_sig value. If none of the values specified are met then the output will get valuen.

    Let's the code for the mux and the decoder:

    For implementation the outputs will be set as LEDs for both the multiplexer and the decoder. The s and i inputs will be slide switches.
    For inputs i0-i3 you can assign constant values in code and see how they are routed to the LEDs with the values from the switches.

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