Link FPGA I/O to entity I/O

    In the last post I showed you how to declare an entity and how to determine the diagram of a circuit from that declaration. Let's consider that we have the architecture written for that entity:
             
                 o<=a and b;


    So o will be the result of input a and input b or a*b. If we were to implement this design in an FPGA the only way to determine if it is correct would be to somehow link those inputs and output to peripherals attached to the FPGA's pins like LEDs and buttons.

    We can do that using a special file called a constraints file. There are two ways to edit constraints:
       - by using the program witch came from the FPGA vendor (ex: Xilinx ISE, Altera Quartus)
       - manually entering the constraints with a text editor

    Before I give you an example of making a constraints file, I will introduce you to the 3 most basic I/O circuits you will use: LEDs, slide switches and push buttons.

    LEDs
    You have probably seen LEDs (Light Emitting Diodes) everywhere. They are small yet bright and come in different colors, but how do they work?

    LEDs, or any diodes, have two elements called anode and cathode and let current flow only in one direction (from the anode to the cathode) so since current flows from positive to negative we can associate the anode with POWER and the cathode with GROUND. By connecting the two sides of an LED to the positive/negative sides of the voltage source, it will light up.

                          
    In the image the LED is properly connected and it will stay lit as long as the power is up. But it's not what we want. We want a way to control when it lights up and when it shuts down. That's why when linked to FPGAs and other electronic devices, LEDs have one of it's components connected to it's respective power source side (anode to POWER and cathode to GROUND) and the other component connected to one of the pins belonging to the device. This way we control the flow of current.
    In most designs the anode is the part connected to the FPGA pin so if we send power (logic 1) to it, the LED lights up and vice versa for logic 0.

    Slide switches
    They are useful if you want to keep something on or off as long as the switch is in the on/off position.

    The picture shows a slide switch connected to a power source:

    The slide switch is an input circuit because it sends a high (1) or low (0) signal to the device it's connected to. The FPGA pin would connect between the resistor and the switch. It means that when it's open, the FPGA receives a high signal because it's linked only to positive (POWER). If the switch is closed then the circuit is complete (POWER-GROUND) and and the FPGA receives a low signal.

    Another way to link a switch is with a resistor placed near ground and the FPGA pin connected between the down side of the switch and the resistor. This means that when the switch is open it sends a low signal and when it's closed it sends a high signal.

    Push buttons

    They have the exact same style of connecting to the FPGA. The only difference is that they send a high/low signal (depending on the connection type) only when pressed.

                                                       

    How it all ties together

    Let's consider an example FPGA witch has 2 switches, 2 buttons and 2 LEDs. Each pin has a name or a code usually composed of letters and numbers. We need that code in order to link it to the proper input/output in the entity. You can find the pin names in your FPGA user manual or schematics.

    In th entity declaration you can see 2 inputs and an output. The outputs is of course an LED. The inputs can be associated with buttons or switches because they are inputs but the reasonable choice is switches. Why? Because we want to maybe have at one time an input low and an input high and keep them that way. If we use buttons then we need to keep one of them pressed as long as we want the low value.

    The example FPGA looks like this:

    

    

    Let's see our entity again:

                 entity andgate is
                    port(
                            a : in std_logic;
                            b : in std_logic;
                            o : out std_logic);
                  end entity andgate;

    As you can see in the picture the pins are named L1 and L2 for the LEDs, SW1 and SW2 for switches and B1 and B2 for buttons. In real FPGAs the codes are not so logical chosen.

    Now it's time to see how a constraint file looks like. We'll connect a to SW1, b to SW2 and o to L1:

                 NET "a" LOC = SW1;
                 NET "b" LOC = SW2;
                 NET "o" LOC = L1;

    As you can see the NET defines our entity I/O and with the LOC keyword we assign it to a real pin on the FPGA.