Monday, October 31, 2011

First VHDL project in Xilinx ISE Webpack

    With the basic understanding of the VHDL program structure and constraints, we can build our first project.

    Downloading Xilinx ISE Webpack
    In my day to day work I use Xilinx ISE Webpack because it's one of the best programs out there for programing FPGAs and lots of other tasks. Plus it's Free! 

    So in order to download the program go to Google and type download xilinx ise webpack and the first result should be the one you are looking for or just go to directly to the download page. Next you will have to choose witch version you want and for witch os (Windows or Linux). At the time I'm writing this tutorial the latest version is 13.3. After clicking on the full installer for windows/linux they require you to make an account on
    The next step after making the account and downloading the software is of course installing it. The process if simple though it might take a long time depending on your computer. Lastly you will need to get a license from xilinx in order to use Webpack. This is done with the help of a program so it shouldn't be to hard.

    Short presentation of the designed circuit
    As you have seen in the last 2 posts we are designing an AND gate. This is a simple logic circuit that takes two inputs and based on their values gives us an output. 

    The symbol truth table for this gate are:

    So the output will be 1 only when both inputs are 1.

    Starting the project
    Let's get started. Launch Xilinx ISE Design Suite on your desktop or from the installation directory on the partition you selected launch ise.exe. In my case the partition is C:/ and the directory is C:\Xilinx\13.2\ISE_DS\ISE\bin\nt.
    After the program launches go to File -> New project. Give your project a name like AndGate and specify a location to store it. Mine is E:\Projects ise\test. Make sure that the Top-level source type is HDL and click Next.


    Now comes the tricky part and unfortunately I can't help you that much. We have to select the dev board properties. If you have purchased it from xilinx odds are you will just have to select it from the Evaluation Development Board menu. If not please check the manual for the info. At Product Category put General Purpose. The device family is easy to find and chances are you have either a Spartan 3 or a Spartan 6. The next two are found in the device manual. For the speed grade I chose the highest value available to me witch is -3. You are free to experiment with it as I didn't find info about it anywhere. The next lines should be exactly like in the picture:

    Click Next and then Finish.
    Now right-click on the name of the project on the upper-left side of the screen and choose New Source:

    Select VHDL Module from the list and give the title andg.

    What we are doing right now is creating the entity from 2 posts ago. So after clicking Next you will be prompted to enter the inputs and outputs.
    You are not obligated to enter those here because they can be manually written in code. 
    For this project let's enter them in the wizard. So we have a and b as inputs and o as an output.

    Click on Next and then Finish. Now our entity is created and the basic VHDL program structure is automatically created.
    The only line you have to enter is: o<=a and b;
    It should go between begin and end Behavioral; and the code should look like this:

    Now it's time to assign the pins through a constraint file. On the left sidebar open the User Constraints tree and select I/O Pin Planing (PlanAhead)-Pre-Synthesis. Right click it and select Run.

    If any question appears after hitting Run select Yes.
    Again here you have to find the pin names for your FPGA and select a LED and 2 slide switches as I showed you in the last post.
    After Plan Ahead opens, in the center of the screen there should be a tree structure like this: All ports -> Scalar ports -> the 3 ports in the entity. Find your pin names and enter them on the Site column like in the picture:

    After that go to File and select Save  Exit PlanAhead.
    The next 3 steps are simple and will not be illustrated. Right-click on Synthesize-XST and select Run. After it is done right click on Implement Design and click Run. Lastly we need to generate a file that programs the FPGA: right-click on Generate Programming File and select Run.
    ISE will generate a file named andg.bit located in the root directory of your project. For me that is: E:\Project ise\test\AndGate. This file contains the code that will program the FPGA's logic blocks and interconnect them if necessary.
    The last part is programming the dev board. If you have a Digilent board then you can use their Adept software. Just plug the device in your PC and select the .bit file. If you are using another board and the drivers for it are installed correctly do the following step to program it with Impact. Open the Configure Target Device tree and right click Manage Configuration Project (iMPACT). Select Run.
    In iMPACT click on File -> New Project and select Yes, then OK. After the software finds your board select the .bit file and click Open. Right click the circuit symbol and select Program.

    Congratulations! You have done your first project.
    I will be uploading a youtube video shortly to show you how it looks on my board.

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