Friday, December 16, 2011

A simple counter

    Counters are very important and you will probably use them in your projects since they are needed in lots of situations. So what do counters do? Very simple: they count. At every clock cycle the value memorized in the counter's memory element is incremented or decremented by 1 and the result is fed to the output port.
    Counter circuits that you can find on the market have different functions like a chip enable input to enable/disable the circuit, parallel load to load a value from the outside and count from there, a port that controls the way it counts (forward or backward). But for the siple projects that we will be designing for now we don't need all those features. All we need is a clock input, a reset input and the data output.
    The value that a counter uses can be of different lengths: 4 bits, 8 bits, 16 bits etc. So when you hear that a counter is a 8 bit counter you will know that the output has 8 bits and so on.
    In this tutorial we will be making a 4 bit bcd counter (it counts from 0000 witch is 0 in decimal to 1001 witch is 9 in decimal). It has of course a 4 bit output for the number and 2 inputs: the clock and the reset.
    How it works: At first the internal value of the counter is 0 so that is what will be at the output. Every clk cycle that value is incremented by 1. Once it reaches 9 (1001), it stays at this value for 1 clk cycle and then goes back to 0. If the reset is activated at any time during the operation of the circuit then the internal value is back at 0.
    Now let's see the code for this counter:

    In order for the code to work you of course have to add the std_logic_unsigned library:
              use IEEE.STD_LOGIC_UNSIGNED.all;

    As you can see it has an asynchronous reset witch when activated resets the cnt variable to all 0s. The output port is refreshed at the end of the process every time.
    Now that we have the code we have to test it. But if we were to put it on the FPGA and connect the clk input to the clock then we wouldn't be seeing results because the clock is to fast (50/100 MHz usually). Let's design a simple test circuit.
    I want this circuit to 1 to the variable every second and display the value on 4 LEDs from the FPGA. For this we will need the clock divider from the previous tutorial in order to obtain a 1 Hz signal from the one that we have (mine is 100 MHz). The output of the divider will connect to the clk input of the counter. This way it is activated every second. The outputs of the counter go directly to 4 LEDs.
    The circuit schematic looks like this:
    So let's begin. To the project with the counter we will add a new entity witch is the divider from the last tutorial. The only difference is that now we want the clko signal to be activated every second, not half a second. For that you just have to double the value used. So for a 50 MHz clock you will use 49000000 and for a 100 MHz clock 99000000.
    Now let's create the main system. As you can tell it has 2 inputs and a 4 bit output:
    We will need just a signal that connects the clko output from the div circuit to the clk input of the counter.
    Let's see the architecture:
    If you want you can modify this project to use a 7 segment display instead of the LEDs. For this you will need to connect the 7 segment decoder to the output of the counter.
    If you want to contact me my e-mail is
    Feel free to leave me suggestions or comments.
    Thank you for reading.


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